Résumé: Clock and Data Recovery (CDR) has been a foundational receiver component in serial communications. Yet this component is known to add significant design complexity to the receiver and to consume significant resources in area and power. In the resource-limited world of constrained IoT nodes, the need of including CDR in the communication link is being re-assessed and new techniques for achieving reliable serial transmission without CDR have been emerging. These new techniques are distinguished by their use of transition edges rather than bit times for coding and detection. This article presents the design, implementation, and testing of a novel CDR-less transmission protocol that achieves significant improvements in data rate, reliability, packet security, and power efficiency with respect to state-of-the-art CDR-less techniques. The new protocol further tolerates significant jitters and clock discrepancies between transmitter and receiver. An FPGA and an ASIC (65 nm technology) implementation of the protocol have shown it to consume around 19? W of power at a clock rate of 25 MHz, and to have a small footprint with a gate count of approximately 2,098 gates. In particular, the new protocol reduces area by more than 87% and power by more than 78% in comparison with CDR-based serial bit transfer protocols. Furthermore, the new protocol is shown to be versatile in its applications to available communication media, including wired, wireless, infrared, and human-body channels, under a variety of digital modulation schemes.

Langue: Anglais