Résumé: Timing of synchronous systems is an everlasting stumbling block to the booming demands for lower power consumption and higher operation speeds in the electronics industry. This hardship is aggravated by the growing levels of variability in state-of-the-art silicon dimensions and in other beyond-CMOS technologies. Although some designers continue to strongly believe in the performance advantages of being fully synchronous, others have radically shifted toward extremely robust delay-insensitive domains. Targeting a different compromise of both performance and robustness, this article provides sufficient conditions for an asynchronous system to be able to generate the periodic signals necessary for the timing of a fully synchronous system and highlights a specific hierarchical clocking structure that with a single tunable delay satisfies these conditions. Using an asynchronous clock distribution network benefits from both the natural robustness of asynchronous structures and the advantageous performance of synchronous clocking.

Langue: Anglais