Résumé: In the past decade, complementary metal oxide semiconductor-memristor hybrid neuromorphic systems have gained importance owing to the advantages of memristors such as nano-scale size, non-volatility, and lowpower operation. However, they are often accompanied by non-ideal properties that can impact the system's performance. This article presents device-aware circuit design to mitigate such effects. A bi-memristor synapse with a robust spike-timing-dependent plasticity (STDP) is designed. A mixed-mode neuron is presented whose accumulation rate is tunable on-chip and can be used with a variety of memristors without needing a re-design. The proposed designs are employed together in an example pattern recognition system. A scalable winner-takes-all circuit is presented for the output stage. A pattern recognition task based on a simple STDP-based learning is demonstrated such that the recognition rate is directly dependent on the learnt weights. Device-level issues such as switching speed/threshold asymmetry, limited switching resolution, endurance, and varying resistance range (across devices) are shown to adversely affect learning at the system level and it is demonstrated that the proposed circuits can mitigate them. Last, the area and energy costs of the proposed designs are evaluated and compared against other implementations in the literature.

Langue: Anglais