Résumé: Traditional memory technologies face severe challenges in meeting the ever-increasing power and memory bandwidth requirements for high-performance computing and big-data analyses. Several emerging memory technologies are promising as the replacements of SRAM or DRAM. Among them, STT-MRAM can be used to replace SRAM as the last-level cache (LLC). However, it suffers from high write energy and latency. In this article,we investigate data patternswritten fromSRAM-based upper-level cache to STT-MRAM-based LLC to explore the write energy reduction potential. Depending on the data layoutwithin a cache line, redundant bits can be identified and eliminated fromwrite back operations to save STT-MRAMwrite energy.We also propose a dynamic profiling method to accommodate different application characteristics. The extensive simulation results show that write energy can be saved by 37.05% ? 38.89% for static profiling and 19.76% ? 34.29% for dynamic profiling.

Langue: Anglais