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Notice détaillée

High performance real-time neural scheduler for ATM switches

Article Ecrit par: Pousada, Carballonjm ; Gonzalez-Castano, F. J. ; Rodriguez, Hernandez, P. S. ; Garcia, Palomares U. M. ;

Résumé: Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, in this paper we formulate and evaluate a new neural scheduler with bounded response time.


Langue: Anglais