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Performance Evaluation and Design Trade-Offs for Wireless Network-on-Chip Architectures

Article Ecrit par: Chang, Kevin ; Pratim Pande, Partha ; Prasad Sah, Suman ; Deb, Sujay ; Ganguly, Amlan ; Yu, Xinmin ;

Résumé: Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.


Langue: Anglais
Thème Informatique

Mots clés:
small-world
NoC
Multicore
wireless links

Performance Evaluation and Design Trade-Offs for Wireless Network-on-Chip Architectures

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